This invention relates to analog readout arrangements and, more particularly, to a hierarchical multiplexer.
The reading out of signals from an analog array element typically is done in serial fashion. Consequently, it is necessary to multiplex signals resulting from the analog array elements one at a time to an output.
Known multiplexers that have been employed in the readout of digital data are the hierarchical multiplexer and the logic decoder type multiplexer. However, in reading out of signals from analog array elements, it is known that use of a hierarchical multiplexer produces so-called fixed pattern noise (FPN). This is undesirable because, for example, in imaging arrays, the resulting FPN from the hierarchical multiplexer causes undesirable streaks in any resulting image. Therefore, logic decoder type multiplexers typically have been employed in multiplexing of signals read out from the analog array elements to an output.
Although the use of the logic decoder type multiplexer may result in less FPN, the logic decoder type multiplexer has other undesirable characteristics. For example, in order to reduce any resulting FPN, each buffer associated with a corresponding element in the analog array must drive the same amount of capacitance, which could become quite large. Since each analog array element and its associated buffer amplifier drive a relatively large capacitance, the resulting amount of drive current is also relatively large. This results in significantly larger power dissipation for the overall analog array, which is extremely undesirable.
These and other problems and limitations of prior known multiplexers for reading out signals from analog array elements are overcome by employing a unique hierarchical multiplexer to multiplex signals read out from the analog array elements one at a time to an output.
In an embodiment of the invention, the multiplexer switching elements, i.e., switches, are arranged in groups in a hierarchical, i.e., tree, configuration. In the tree configuration for a given analog array size, output capacitance is significantly reduced because each analog array element and its associated buffer amplifier drive fewer switches than in other configurations. The lower capacitance reduces any resulting FPN and the resulting lower analog array element and buffer amplifier drive current reduces power dissipation. The reduced capacitance also decreases the transient settling time interval.
In one embodiment of the invention, a hierarchical multiplexer employed in reading out signals from elements of an analog array is optimized to produce low FPN by employing unity gain buffer amplifiers which are associated on a one-to-one basis with the analog array elements; using offset correction to compensate for nonuniformity of offset voltages or currents among the buffer amplifiers; not allowing direct current (DC) to flow in switches utilized in the multiplexer; and allowing all transients to settle prior to reading out signals from the analog array elements.
In a specific embodiment of the invention, the offset compensation is effected for signals being read out from each element of the analog array by sampling and storing a first value representative of a xe2x80x9cregularxe2x80x9d output from the multiplexer that is associated with a particular array element and its associated buffer amplifier, sampling and storing a second value representative of a reference output, i.e., an output from the multiplexer resulting from a reference potential being supplied to the buffer amplifier input associated with the particular analog array element, and subtracting the second value from the first value to yield an offset compensated output.